1. Field of the Invention
This invention relates to a parallel-to-serial converter intended to serialize a data signal that is phase shifted with regard to a local clock signal.
Typically a parallel-to-serial converter comprises a bus receiving incoming parallel data from a processing device and reproduces this data in serial form in a transmission medium. Such a converter comprises at least one parallel-to-parallel register and one parallel-to-serial register.
These two registers are constituted of logic flip-flops and are connected in cascade in the converter. The parallel-to-parallel register receives incoming parallel data which it then transfers, at the rate of a first clock signal, to an output bus applied to inputs of the parallel-to-serial register. The parallel-to-serial register is loaded at the rate of a second clock signal by this transferred data which is then serialized for transmission in the transmission medium.
2. Description of the Prior Art
According to the prior art, the first and second clock signals having the same frequency are independent of each other in terms of phase. Indeed according to conventional embodiments, a phasor is provided in the converter to generate the first clock signal which rhythms the transfer of data outgoing from the parallel-to-parallel register whereas a time base in the converter provides the second clock signal independently of the first clock signal. The phasor is used to generate the first clock signal with a phase which is a function of the phase of the incoming parallel data. Since both registers are essentially designed with logic flip-flops, their operation depends on logic transition times (rising or falling edges) of the clock signals. It is natural, therefore, at high transfer rates, that times of transfer of incoming parallel data to the outputs of the parallel-to-parallel register coincide with loading times for this data at the outputs of the parallel-to-parallel register in the parallel-to-serial register. In this precise situation, loading of the parallel-to-parallel register can lead to loss of data due to the fact that sampling times concerning loading of data into the parallel-to-serial register do not correspond to durations during which the data are stable at the outputs of the parallel-to-parallel register.